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CYNCP80192
CYNCP80192 Network Database Coprocessor
Cypress Semiconductor Corporation Document #: 38-02043 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised August 27, 2003
CYNCP80192
CONTENTS 1.0 OVERVIEW ...................................................................................................................................... 5 2.0 FEATURES ...................................................................................................................................... 6 3.0 FUNCTIONAL DESCRIPTION ......................................................................................................... 7 3.1 Configuration Registers .............................................................................................................. 7 3.2 Operating Registers .................................................................................................................... 7 3.3 Pipeline and Table Management and Bus Protocol Conversion Logic ....................................... 7 3.4 NSE Interface .............................................................................................................................. 7 3.5 Associative SSRAM Interface ..................................................................................................... 7 4.0 SIGNAL DESCRIPTION ................................................................................................................... 8 5.0 CLOCKS ......................................................................................................................................... 11 6.0 REGISTERS ................................................................................................................................... 12 6.1 Coprocessor Interface Register ................................................................................................ 12 6.2 Configuration and Status Registers .......................................................................................... 12 7.0 OPERATING REGISTERS ............................................................................................................. 15 7.1 Address Mapping ...................................................................................................................... 15 7.2 Context Descriptor Organization ............................................................................................... 16 7.3 Context Descriptor Commands ................................................................................................. 16 8.0 NDC SUBSYSTEM POWER-UP INITIALIZATION PROCEDURE ................................................ 23 9.0 ZBT PIPELINED SSRAM INTERFACE MODE ............................................................................. 24 10.0 ZBT FLOWTHROUGH SSRAM INTERFACE MODE .................................................................. 25 11.0 SYNCBURST PIPELINED SSRAM INTERFACE (EARLY WRITE) ............................................ 26 12.0 SYNCBURST PIPELINED SSRAM INTERFACE MODE (LATE WRITE) ................................... 27 13.0 APPLICATION INFORMATION ................................................................................................... 28 14.0 INFORMATION ON EXTERNAL TRANSCEIVERS .................................................................... 29 15.0 JTAG (1149.1) TESTING ............................................................................................................. 30 16.0 ELECTRICAL CHARACTERISTICS ............................................................................................ 31 17.0 ORDERING INFORMATION ........................................................................................................ 39 18.0 PACKAGE DRAWINGS ............................................................................................................... 40
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CYNCP80192
LIST OF FIGURES Figure 2-1. CYNCP80192 Block Diagram ............................................................................................... 6 Figure 5-1. NDC Clocks......................................................................................................................... 11 Figure 9-1. ZBT Pipelined SRAM Interface (Mode 000) ........................................................................ 24 Figure 10-1. ZBT Flowthrough SSRAM Interface (Mode 001)............................................................... 25 Figure 11-1. SyncBurst Pipelined SSRAM Interface (Early Write) ........................................................ 26 Figure 12-1. SyncBurst Pipelined SSRAM Interface (Late Write).......................................................... 27 Figure 13-1. Configuration 1--Associative SSRAM Mode .................................................................... 28 Figure 13-2. Configuration 2--Index Mode............................................................................................ 28 Figure 13-3. Switching Systems Block Diagram .................................................................................... 28 Figure 14-1. Use of Transceiver Enables .............................................................................................. 29 Figure 14-2. Transceiver Connected Between CYNPC80192 and CYNSE70XXX Devices ................. 29 Figure 16-1. Pinout Diagram.................................................................................................................. 33 Figure 18-1. Package Bottom View ....................................................................................................... 40 Figure 18-2. Package Side View ........................................................................................................... 40 Figure 18-3. Package Top View ............................................................................................................ 41
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CYNCP80192
LIST OF TABLES Table 4-1. Search Coprocessor Pin Description ..................................................................................... 8 Table 6-1. Register Partitions for Coprocessor Access ........................................................................ 12 Table 6-2. Configuration and Status Registers Area ............................................................................ 12 Table 6-3. Configuration Register ......................................................................................................... 12 Table 6-4. Error and Status Register .................................................................................................... 13 Table 6-5. Error Codes ......................................................................................................................... 13 Table 6-6. Information Register Description ......................................................................................... 14 Table 7-1. Operating Registers Addressing Mapping (ADR[9] = 1) ...................................................... 15 Table 7-2. Context Descriptor Organization ......................................................................................... 16 Table 7-3. Descriptor Command ........................................................................................................... 16 Table 7-4. Read Command .................................................................................................................. 18 Table 7-5. Write Command ................................................................................................................... 18 Table 7-6. Search Data ......................................................................................................................... 18 Table 7-7. Move Command Parameters ............................................................................................... 19 Table 7-8. Swap Command Parameters .............................................................................................. 19 Table 7-9. SSRAM Data ....................................................................................................................... 19 Table 7-10. NSE Data, Mask, and Register Locations ......................................................................... 19 Table 7-11. Read Response at Result Register 0 ................................................................................ 19 Table 7-12. Data Read from NSE ......................................................................................................... 20 Table 7-13. Data Read from SSRAM ................................................................................................... 20 Table 7-14. Write/Move/Swap/Learn Results Register 0 ...................................................................... 20 Table 7-15. Result Register 0 for Search Operation ............................................................................. 21 Table 7-16. Result Register 1 (Search Result Bit in Data Field = 0) ..................................................... 21 Table 7-17. Result Register 1 (Search Result Bit in Data Field = 1) ..................................................... 21 Table 7-18. Search Response in Result Register 0 (type I) ................................................................. 21 Table 7-19. Index Bits for NSEs ........................................................................................................... 22 Table 15-1. Test Access Port Controller Instructions ........................................................................... 30 Table 15-2. Test Access Port Device ID Register ................................................................................ 30 Table 16-1. Electrical Characteristics ................................................................................................... 31 Table 16-2. Capacitance ....................................................................................................................... 31 Table 16-3. Operating Conditions ......................................................................................................... 31 Table 16-4. AC Timing Parameters for Pipelined ZBT SSRAM and SyncBurst SSRAM ..................... 31 Table 16-5. AC Timing Parameters for ZBT and Flow-Through SSRAM ............................................. 32 Table 16-6. CYNPC80192 Pinout Description ...................................................................................... 34 Table 17-1. Ordering Information .......................................................................................................... 39
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CYNCP80192
1.0 Overview
Cypress Semiconductor Corporation's (Cypress's) network database coprocessor (NDC) performs the following three primary functions. * Interconnection bridge function. The CYNCP80192 device acts as a bridge between network processor(s) and a search subsystem of Cypress's CYNSE70XXX network search engines (NSEs) plus optional associated SSRAMs that contain a search database and the associated data for a variety of network protocol layers. The CYNCP80192 device interfaces to the network processor with an SSRAM interface and offloads the search function to provide support for fast packet processing in routers and switches. * Pipeline management function. Cypress's NSEs have a pipelined architecture to optimize search performance and throughput. The CYNCP80192 device manages the pipeline for optimal search performance and packs instructions back to back in order to avoid any bubbles in the pipeline. * Table management function. The CYNCP80192 device builds on the simple instructions of the NSEs to provide advanced instructions for table management. There are two ways to build the NDC system. * In the first system the associative data SRAMs are connected to the CYNCP80192 device and the NSE(s) (see "NDC Subsystem Power-up Initialization Procedure" on page 23), and the CYNCP80192 device returns the associated data in response to a search operation. This type of implementation is suited to applications where the associative data size is up to eight bytes. * In the second system, the CYNCP80192 device returns the index of the successful search entry to the network processor. The network processor uses this index to access SSRAMs in order to get the required results. The SSRAMs containing the associative data are connected directly to the network processor's SSRAM bus. This is suitable for applications where the associative data size is longer than eight bytes. The NDC runs up to 100 MHz. At that speed and running with a 64-bit bus interface, the NDC performs at a peak rate of 33 million searches on 68-bit entries, 25 million searches on 136-bit entries, and 16.67 million searches on 272-bit entries. At 100-MHz speed and running with a 32-bit bus interface, the NDC performs at a peak rate of 25 million searches on 68-bit entries, 16.67 million searches on 136-bit entries, and 10 million searches on 272-bit entries. The NDC supports centralized, multiple layer, multiwidth tables in order to provide cost effective search solutions for Ethernet, asynchronous transfer mode (ATM), and Sonet-based switches and routing systems. It supports the following advanced capabilities: quality of service (QoS), class of service (CoS), virtual private network (VPN), packet and flow classification, and security.
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CYNCP80192
2.0 Features
* The hardware interface to the NDC uses an SSRAM interface. The CYNCP80192 device supports ZBT pipelined, ZBT flowthrough, and SyncBurst pipelined (late and early write) types of SSRAMs. * All instructions and/or responses are mapped into the SSRAM address (ADR) space. * The CYNCP80192 device provides simultaneous multiple layer, variable-width tables (x68, x136, x272). * There is support for table sizes up to four million x34 entries. * There are 33 million searches per second (Msps) in the x68 configuration (CFG). * The CYNCP80192 device is compatible with 1-Mb, 2-Mb, and 4-Mb NSEs. * It has a glueless interface to industry standard synchronous SRAMs and NSEs. * The CYNCP80192 device uses up to 100 MHz master clock frequency. * It has an IEEE 1149.1 test access port. * There is a 2.5V/3.3V power supply and a 388-pin BGA package. The CYNPC80192 NDC contains the following function blocks, shown in Figure 2-1.
Network Processor Interface (SSRAM bus)
Configuration Register Data Operating Register
Pipeline and Table Management, and Bus Protocol Conversion Controller
NSE Interface SADR
NSE
[1]
Return ID
Associative SSRAM Interface
SDATA
[1]
SSRAMs
Figure 2-1. CYNCP80192 Block Diagram
Note: 1. 1. The device can be configured for returning SADR or SDATA.
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CYNCP80192
3.0
3.1
Functional Description
Configuration Registers
The CFG registers contain information for configuring the CYNPC80192. These registers also include error, status, mask, and information registers.
3.2
Operating Registers
This logic block contains the random access registers through which the network processor(s) perform most of the table programming, management functions, and search operations (via a request-response protocol). A network processor posts operation requests and Reads responses back from this access block.
3.3
Pipeline and Table Management and Bus Protocol Conversion Logic
This unit uses pipeline management logic to optimize the search performance through the NSE pipeline. This unit posts the commands to the NSE and steers the results to the appropriate locations in the operating registers. It also converts the SSRAM interface information from a network processor into protocol cycles of the NSE transactions. This unit builds on the commands provided by the NSE to provide more advanced table management commands to the network processor.
3.4
NSE Interface
This interface generates the appropriate hardware handshake with the NSE(s). This block is a slave to the pipeline control unit and drives the NSE(s) bus with the appropriate commands.
3.5
Associative SSRAM Interface
The data transfer between the SSRAM and the pipeline unit takes place in this interface. The pipeline unit further transfers this information to the operating registers.
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CYNCP80192
4.0 Signal Description
Table 4-1 provides information on pins and signal names for the CYNCP80192 device. Under the "Type" heading, I = Input, O = Output, and T = three-state. Table 4-1. Search Coprocessor Pin Description Parameter IRST_L CLK[2] ADR[9:0] Type I I I Description Synchronous Reset Input. Active low. Initializes the device to a known state. Coprocessor Clock Input. CLK may be run up to 100 MHz. Coprocessor Location Address. This 10-bit address bus ADRs up to 1024 32-bit locations in the coprocessor. These 1024 locations are further divided into 512 32-bit locations of CFG area and 512 32-bit locations of the operating register area. When the data bus is configured as 64 bits wide (using the IWIDTH pin described below), the ADR[0] is ignored by the device. When the data bus is configured as 32 bits wide (using the IWIDTH pin described below), all the ADR bits are used by the device. Coprocessor Data Bus. Only the [31:0] field of this bus is used when the coprocessor is configured for a 32-bit interface (using the IWIDTH pin described below). Coprocessor Chip Enable. This active low signal is used to enable the device. This is one of the three chip enables (CEs) to the coprocessor. All three CEs must be active to select the coprocessor. Coprocessor Chip Enable. This active low signal is used to enable the device. This is another one of the three CEs to coprocessor. All three CEs must be active to select the coprocessor. Coprocessor Chip Enable. This active high signal is used to enable the device. This is another one of the three CEs to the coprocessor. All three CEs must be active to select the coprocessor. Read/Write. This input determines whether it is a Read or a Write cycle. A low on this pin means it is a Write operation, and a High means it is a Read operation. Coprocessor Output Enable. This active low asynchronous signal enables the output drivers of the data bus. Synchronous Byte Write Enables. These active low signals allow individual bytes to be written when a Write cycle is active. When the data bus is configured as 32 bits wide, only BW_L[3:0] is used and the BW_L[7:4] should be tied to VDD externally. Byte Write Enable. This active low signal allows the byte Write signals (BW_L[7:0]) to control the Write operation. When the done bit is set in result register 0, STRB qualifies the CPID[7:0]. The network processor can use STRB signal to latch the CPID signals. Context ID and Processor ID. When the result is Ready in the descriptor, the NDC outputs the processor and context IDs are concatenated as follows: {processor ID, context ID}. The bit length of the processor and context IDs can be programmed using the CFG register 0 (see CPCFG). See the STRB signal description also. This interrupt pin is asserted when the SE_FULL, DESC_AFULL, or error bits filed is set in the error status register. Interrupt can be active high or low, depending upon the polarity selected in the CFG register. NSE table full indicator to the network processor. This bit indicates that the descriptor array is almost full. When this flag is set, the processor can send only two more commands to the descriptor. The DESC_AF flag will be cleared if more that two descriptors are available. NSE Master Clock. CYNPC80192 drives this CLK to the NSE. The frequency of this CLK is twice the frequency of the NSE. This CLK runs up to 100 MHz and is derived by buffering the input CLK at the coprocessor interface. Phase Signal to the NSE. This signal runs at half the frequency of CLK2X and synchronizes the alignment of the instruction to the NSE. Network Processor Interface
DATA[63:0] CE_L CE2_L CE2 R/W_L OE_L BW_L[7:0]
IO I I I I I I
BWE_L STRB CPID[7:0]
I O O
INTR/INTR_L
O
SE_FULL DESC_AFUL
O O
NSE Command and DQ Bus CLK2X O
PHS_L
O
Note: 2. "CLK" is an internal clock signal.
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CYNCP80192
Table 4-1. Search Coprocessor Pin Description (continued) Parameter ORST_L CMD[8:0] Type O O Description Reset Output to the NSE. Driving ORST_L low initializes the NSE. Command Bus to the NSE. Bits [1:0] specify the command and [8:2] contain the command parameters. The descriptions of individual commands explain the details of the parameters. The encoding of commands based on the [1:0] field are: 00: Read; 01: Write; 10: Search; 11: Learn. Command Valid to the NSE. Qualifies the CMD bus. 0: No command. 1: Command valid. NSE Address/Data Bus. This signal carries the Read and Write address and data during register, data, and mask array operations. It carries the compare data during search operations. It also carries the SSRAM address during SSRAM accesses to the SSRAMs containing the associative data. When the CYNSE70128 NSE is used, the four additional DQ bits DQ[68:71] on the CYNSE70128 should be connected to the DQ_72 output from the CYNPC80192. The DQ_72 signal is driven low from the CYNPC80192. Read Acknowledge. This signal indicates that valid data is available on the DQ bus during register, data, and mask array Read operations to the NSE, or that the data is available on the SRAM data bus during Read operations of the SRAM containing associative data. End of Transfer. This signal indicates the end of a burst transfer during Read or Write burst operations to the NSE. Search Successful Flag. This signal indicates that the search was successful in the NSE bank. Search Successful Flag Valid. When asserted, this signal qualifies the SSF signal. NSE entries full indicator. Transceiver enable for driving signals to the NSE. Active high.[3] Transceiver enable for driving signals from the NSE. Active low.[3] Transceiver enable for driving signals to the NSE. Active high.[3] Transceiver enable for driving signals from the NSE. Active low.[3] Transceiver enable for driving signals to the NSE. Active high.[3] Transceiver enable for driving signals from the NSE. Active low.[3] SRAM Data/Address. This bus contains either the data from the associative SSRAM or the ADR (Index) from an NSE, depending on the value of the SRAM present bit in CFG register 0. {SDATA[63:0]} from SSRAMs should be connected to the 64-bit bus if the associative SSRAM is present, or else {SADR[23:0]} from the NSEs should be connected to the 64-bit bus. SSRAM Output Enable. This signal is the output enable control for the off-chip SSRAM bank that contains associative data and is driven by the NSE. SSRAM Clock. This is the same in phase and frequency as the one created internally by the NSE. It is generated by dividing CLK by two, and is used to drive the SSRAM CLK input. This signal selects coprocessor data bus width. 1: 64 bits; 0: 32 bits. This selects how data from the network processor is interpreted. 1: Big Endian; 0: Little Endian. This signal selects coprocessor interface type: 000: ZBT pipelined mode 001: ZBT flowthrough mode 010: SyncBurst pipelined mode (early Write) 011: SyncBurst pipelined mode (late Write) 100-111: Reserved.
CMDV
O
DQ[67:0]
IO
DQ_72
IO
ACK
I
EOT SSF SSV FULL XVER_0 XVER_0_L XVER_1 XVER_1_L XVER_2 XVER_2_L SDATA[63:0]/ SADR[23:0]
I I I I O O O O O O I/O I/O
Associated SRAM Interface
SOE_L SCLK Configuration IWIDTH BIG/LTL_L IFC_CFG[2:0]
I O
I I I
Note: 3. Detailed information on the external transceiver is given in "Information on External Transceivers" on page 29.
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CYNCP80192
Table 4-1. Search Coprocessor Pin Description (continued) Parameter TDI TCK TDO TMS TRST_L Type I I T I I IEEE 1149 JTAG test data in. IEEE 1149 JTAG test clock. IEEE 1149 JTAG test data out. IEEE 1149 JTAG test mode select. IEEE 1149 JTAG reset. Description Test Access Port
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CYNCP80192
5.0 Clocks
The CYNPC80192 receives up to a 100-MHz master CLK at the coprocessor interface. The CYNPC80192 then generates the CLK2X and a phase signal PHS_L for the NSEs, and the SCLK for the associative data SSRAMs, as shown in Figure 5-1.
Input CLK to CYNPC80192
CLK
Input signals CLK2X for NSEs PHS_L CLK for SSRAMs SCLK Figure 5-1. NDC Clocks
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CYNCP80192
6.0
6.1
Registers
Coprocessor Interface Register
The network processor(s) access the NDC using the coprocessor (SSRAM) interface. The NDC has a CFG and status registers area and an operating registers area, as shown in Table 6-1. Table 6-1. Register Partitions for Coprocessor Access Address 0-511 Abbreviation CFG and Status Registers Type R/W Description These registers are for configuring the NDC (Read/Write), reporting the error code in the status register (Read-only), setting up the mask register for asserting INTR (Read/Write), and obtaining information on the device (Read-only). Dynamic access for searches and table management happens through this area of the coprocessor address space.[4]
512-1023 ADR[9] = 1
Operating Registers
R/W
The CFG area shown in Table 6-2 is used for programming the NDC via a 64-bit CFG register.[5] Table 6-2. Configuration and Status Registers Area Address 0-1 2-3 4-5 6-7 8-9 10-511 CFG Register Error, Status Registers (Read-only) Mask Registers Reserved Information Registers (Read-only) Reserved Configuration and Status Registers Area
6.2
6.2.1
Configuration and Status Registers
Configuration Register
The 64-bit CFG register contains the following fields, as shown in Table 6-3. Table 6-3. Configuration Register Configuration Register [63:0] ADR 0-1 63-12 Reserved 11 External Transceiver Present 10 Search Result Bit in Data Field 9 INTR_Polarity 8 SSRAM Present 7-6 CPCFG 5-3 HLAT 2-1 TLSZ 0 SRST
SRST. This active high bit resets the state of the device. The reset bit will be active for 32 CLK cycles and will be automatically cleared after the reset has taken effect. Table Size (TLSZ). This determines the NSE CFG for the specific table size.[6] Latency of Hit Signals (HLAT). This determines the data access latency of associated data SSRAM.[7] CPCFG. This field sets the width of the processor and context IDs that will be driven on the CPID bus after the completion of the operation. The contents of the CPID bus are generated by concatenating LSBs of the processor ID and the LSBs of the context ID. 00: CPID[7:0] = {processor ID[2:0], context ID[4:0]}. 01: CPID[7:0] = {processor ID[3:0], context ID[3:0]}. 10: CPID[7:0] = {processor ID[4:0], context ID[2:0]}. 11: Reserved.
Notes: 4. The resulting registers of the context descriptors are Read-only. 5. Once the NDC is configured, the network processors will use the operating registers area to configure the NSEs, initialize and manage the protocol layer tables, and perform searches through such tables. 6. Though the NDC does not program the NSE with this information, the coprocessor uses it to determine the duration of operations such as Search and Learn. (More details on this field can be found in the data sheets for CYNSE70XXX NSEs.) 7. Though the NDC does not program the NSE with this information, the coprocessor uses it to determine the duration of operations such as Search and Read from the SSRAMs. (More details on this field can be found in the data sheet on CYNSE70XXX NSEs.)
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CYNCP80192
SSRAM Present. This field informs the coprocessor whether the associative data SSRAM is connected to the NSE (bit is set to 1; see Figure 13-1) or connected to the network processor SRAM interface (bit is set to 0; see Figure 13-2). INTR_Polarity. This bit controls the polarity of the INTR/INTR_L signal. When this signal is high, the INTR/INTR_L signal is active high. When this signal is low, the INTR/INTR_L signal is active low. Search Result Bit in Data Field. If this bit is set to 1, the Hit or Miss information will be attached to the associative data field in bit 63. This bit has significance only when associative SSRAM is present (see Result Register 1 for the Search command). This bit does not replace the hit bit located in Result Register 0. External Transceiver Present. If an external transceiver is used to drive several NSE devices, this bit should be set to 1. 6.2.2 Error and Status Register
The error and status register is 64 bits wide. Table 6-4 shows the bit positions of the error status register. The errors shown in Table 6-5 will be detected by the NDC and the corresponding error bit will be set in the error and status register. Once it is Read, the error and status register will be cleared. Error Bits. The error bits field holds the type of error. In the case of multiple errors, multiple error bits may be set. The context descriptor index will contain the index where the last error occurred. When an error occurs, the error bit is set along with the done bit in Result Register 0. The class and type of error (soft error [SE] or hard error [HE]) are indicated in the error and status register. When an error occurs, the INTR signal is asserted and a corresponding error bit is set along with the context descriptor index to identify the erroneous command. The interrupt signal is programmable as active low or active high depending upon the system requirement. See the description of the CFG register for further detail. Table 6-4. Error and Status Register 63-32 Reserved 31 HE 30 SE 29 SE_FULL 28 DESC_FULL 27 DESC_AFULL 26-13 Reserved 12-8 Context Desc Index 7-0 Error Bits
Table 6-5. Error Codes Error Bit 0 1 2 3 4 5 6 7 Invalid Command (SE) Reserved Reserved Search or Learn size invalid (i.e., 11 in search size field is not allowed) (SE) NSE access time out (HE) Reserved Reserved Reserved Error Description
Context Descriptor Index. This field identifies the context descriptor that caused the last error condition. In the case of multiple errors, this field will be overwritten. DESC_AFULL. This bit indicates that the descriptor array is almost full. When this flag is set, the processor(s) can send only two more commands to the descriptors. The DESC_AF flag will be cleared if more that two descriptors are available. DESC_FULL. This bit indicates that the descriptor array is full. When this flag is set, the processor can send no commands to the descriptor. The DESC_FULL flag is cleared upon Reading the status register. SE_FULL.[8] This bit indicates that the table in the NSE is full. SE. The SE bit indicates that the error is recoverable and that the command has to be reissued. HE. The HE bit indicates that the error is not recoverable, and that the coprocessor has to be reset and reinitialized by the software before further operations are attempted. 6.2.3 Mask Register
The mask register is 64 bits wide. The bits in this field can be used to mask the INTR generated by any of the bits set in the error and status register. Setting the bits in this register causes the interrupt to be masked. The default value in the mask register is FFFFFFFF (lower 32 bits only).
Note: 8. SE_FULL may be altered as a result of executing a Learn or Write command by the NSE. This flag will be cleared upon reading the status register.
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CYNCP80192
6.2.4 Information Register The information register is 64 bits wide. Table 6-6 describes the lower-order 32 bits in the information register. It uses ADRs 8 and 9 of the CFG register area. Table 6-6. Information Register Description ADR 8 Field Revision Implementation Device ID MFID 9 - Range [3:0] [6:4] 7 [15:8] [31:16] [63:32] Initial Value 0001 001 0 00000011 1101_1100_ 0111_1111 - Description Revision Number. This is the current device revision number. Numbers start at one and increment by one for each revision of the device. This is the CYNPC80192 implementation number. Reserved. Product code for CYNPC80192. Manufacturer ID. This field is the same as the manufacturer ID used in the TAP controller. Reserved.
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CYNCP80192
7.0 Operating Registers
There are 512 uniquely addressable 32-bit-wide registers (see Table 7-1). These 512 registers are divided into 32 descriptors and are called context descriptors (or "context"). Each context comprises 16 registers (i.e., 32 x 16 = 512). Each of these contexts is used for storing commands, data, and responses (returned results from NSEs). These 32 contexts provide a 32-deep pipeline for the network processor(s) system. The allocation of contexts between the multiple processors (or one processor running multiple processors) can be done by the network processor system. For example, a network processor system having four processing elements can assign eight contexts for each processor.
7.1
Address Mapping
ADR[8:0] 0-15 16-31 32-47 48-63 64-79 80-95 96-111 112-127 128-143 144-159 160-175 176-191 192-207 208-223 223-239 240-255 256-271 272-287 288-303 304-319 320-335 336-351 352-367 368-383 384-399 400-415 416-431 432-447 448-463 464-479 480-495 496-511 Contents Context 0 Context 1 Context 2 Context 3 Context 4 Context 5 Context 6 Context 7 Context 8 Context 9 Context 10 Context 11 Context 12 Context 13 Context 14 Context 15 Context 16 Context 17 Context 18 Context 19 Context 20 Context 21 Context 22 Context 23 Context 24 Context 25 Context 26 Context 27 Context 28 Context 29 Context 30 Context 31
Table 7-1. Operating Registers Addressing Mapping (ADR[9] = 1)
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7.2 Context Descriptor Organization
Table 7-2 shows the organization of the context descriptor. During normal operation, the network processor Writes in the context descriptor block (addresses 0-9 within the block) with the command and the appropriate data and Reads the results from the context descriptor block (addresses 12-15 within the block). Note. In 64-bit bus mode, the even and the next odd location are accessed in the same cycle, and ADR[0] is ignored. Table 7-2. Context Descriptor Organization ADR 0-1 2-3 4-5 6-7 8-9 10-11 12-13 14-15 Context Descriptor Organization Command Descriptor Data 0 Data 1 Data 2 Data 3 Reserved Result Register 0 Result Register 1 Access R/W R/W R/W R/W R/W -- R R
Depending on the type of command, the network processor may only need to Write to selected locations of Data 0-3, and may only need to Read from selected locations of Result Register 0 or 1. Note. Addresses 0-9 are Read/Write and addresses 12-15 are Read-only locations.
7.3
Context Descriptor Commands
This 64-bit word (eight bytes) describes the command to the coprocessor. The contents of each of these eight bytes and a description of each of these fields are described below in Table 7-3. Table 7-3. Descriptor Command Bit Positions 7 63-56 55-48 47-40 39-32 31-24 23-16 15-8 7-0 Reserved Reserved Reserved 6 Reserved Reserved Search Successful Register Index SSRAM Address Prefix Direct/Indirect Access Location Layer Attribute/Valid Bit for Data 3 Layer Attribute/Valid Bit for Data 1 Command Reserved 5 Field Description 4 3 2 Context ID Processor ID Global Mask Index Comparand Register Index Search Size Start Layer Attribute/Valid Bit for Data 2 Layer Attribute/Valid Bit for Data 0 1 0
Context ID. This field contains the context ID that a network processor has assigned to this specific context. Processor ID. This field contains the ID number of the network processor that wrote the descriptor. Global Mask Index. This field is used only for Search, Write, Move, and Swap commands to the NSE(s). This field selects one of the eight global mask register (GMR) pairs from the NSE bank for Search, Write, Move and Swap commands. In the case of a 272-bit search, two pairs of GMRs are used. These two pairs include one that is specified in the command and other is a subsequent pair. For example, if the GMR pair 7 is specified, the GMR pair 0 will be used as the subsequent pair for 272-bitwide searches. Search Successful Register Index. The search successful register (SSR) index field is used only for Search and Write operations to the NSEs. Up to eight search successful indexes are stored in each of the NSEs. This field selects one of those eight registers for the Search and indirect Write operations to the NSEs. (Refer to the data sheet specifications of the CYNSE70XXX devices for further information.) Comparand Register Index. This field is used only for Search and Learn operations. This field specifies the comparand register in each of the NSEs that will store the comparands (as they are searched). A subsequent Learn instruction can insert the stored comparands in a table residing in the NSE(s). (Refer to the data sheet specifications of CYNSE70XXX devices for further information.)
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SSRAM Address Prefix. In the implementation with a SSRAM connected to the NSE (see Figure 13-1), these three bits are used as an SSRAM address prefix (SAP) to generate the address of the associative SSRAM. (Refer to the data sheet specifications of the CYNSE70XXX devices for further information.) Start. When the command and associated parameters have been written to the command descriptor, a process running on the network processor can set this bit to initiate the operation by the CYNPC80192. Search Size. This two-bit field is used only by Search and Learn instructions and describes the word size for these operations. Note. Learn command is not supported in the 272-bit wide table. The following describes the data that will be presented to the NSE for various search sizes. 000: x68 ({Data 0, layer attribute/valid bit for Data 0}) 001: x136 ({Data 1, layer attribute/valid bit for Data 1; Data 0, layer attribute/valid bit for Data 0}) 010: x272 ({Data 3, layer attribute/valid bit for Data 3; Data 2, layer attribute/valid bit for Data 2; Data 1, layer attribute/valid bit for Data 1; Data 0, layer attribute/valid bit for Data 0}. Note. The two-bit search size must contain 00 for non-Search/Learn instructions. Access Location. This two-bit field is used by Read, Write, Move, and Swap instructions, and indicates the region accessed in the NSEs or the associative data SSRAMs. 000: NSE data array. 001: NSE mask array. 010: SRAM connected to the NSE. 011: NSE internal registers. Direct/Indirect. This one-bit field is used by Read and Write instructions and controls the address generation to the NSEs and the associated data SSRAMs. When this bit is set, it specifies indirect addressing using SSRs in the NSEs. (Refer to the specifications of CYNSE70XXX for further information.) Layer Attribute and Valid Bit for Data 0. This field contains the three-bit layer attribute as well as a valid bit to accompany data in the Data 0, in the context descriptor. The layer attributes bits may be used for maintaining multiple search tables (of different widths) in the NSE(s). However, if multiple search tables are not used, these bits can be used for any purpose. Layer Attribute and Valid Bit for Data 1. This field contains a three-bit layer attribute as well as a valid bit to accompany data in the Data 1, in the context descriptor. The layer attributes bits may be used for maintaining multiple search tables (of different widths) in the NSE(s). However, if multiple search tables are not used, these bits can be used for any purpose. Layer Attribute and Valid Bit for Data 2. This field contains the three-bit layer attribute as well as a valid bit to accompany data in the Data 2, in the context descriptor. The layer attributes bits may be used for maintaining multiple search tables (of different widths) in the NSE(s). However, if multiple search tables are not used, these bits can be used for any purpose. Layer Attribute and Valid Bit for Data 3. This field contains the three-bit layer attribute as well as valid bit to accompany data in the Data 3, in the context descriptor. The layer attributes bits may be used for maintaining multiple search tables (of different widths) in the NSE(s). However, if multiple search tables are not used, these bits can be used for any purpose. Commands. NDC currently supports six basic commands. Command bits 7 through 3 are reserved and must be programmed as 0s for the following commands: 000: Read 001: Write 010: Search 011: Learn 100: Move 101: Swap. 7.3.1 Command Description and Parameters
Read Command (00 H). Table 7-4 shows the format for the Read command. The Read command's structure is rd(ADR). The Read command uses two 64-bit words in the context descriptor, command descriptor word, and Data 0 word. The Read command is issued through the command descriptor. The Read access location, either data array, mask array, NSE register, or external SSRAM is encoded in the command descriptor word. Bits 15-0 of the Data 0 word contain the Read address. Bits 23-19 of the Data 0 word supply the NSE ID (SEID).
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Result Registers 0 and 1 return the result of the Read operation in two 64-bit words. Table 7-4. Read Command Address Data 0 63-24 Reserved 23-19 SEID 18-16 Reserved 15-0 Address Pointer
Write Command (01 H). Table 7-5 shows the format for the Write command. The Write command's structure is wr(ADR, dt). The Write command uses three 64-bit words in the context descriptor: command word, Data 0 word and Data 1 word. The Write command is issued through the command descriptor. The Write access location could be either the data array, mask array, NSE register or associative SSRAM connected to the NSE. Bits 15-0 of the Data 0 word contain the Write address. Bits 23-19 of the Data 0 supply the SEID. The Data 1 word contains the data bits [67:4], while the data bits [3:0] (called layer bits for Data 1) are passed in the command descriptor word. Table 7-5. Write Command Address Data 0 Data 1 63-24 Reserved 23-19 SEID Data [67: 4] 18-16 Reserved 15-0 Address Pointer
Search Command (02H). The Search command's structure is se(dt0) for 68-bit word, se(dt0,dt1) for 136-bit word and se(dt0,dt1,dt2,dt3) for 272-bit word. The Search command uses two, three, or five 64-bit words in the context descriptor depending upon the size of the search entry (68-bit, 136-bit, or 272-bit). The search size is encoded in the command word, bits [26:25]. Data bits [3:0] for each 68-bit NSE word are stored in the command word in layer attribute bits for Data 0 through Data 3. The number of layer attribute bits used in the command word depends upon the search size. Thus, for a 68-bit search the descriptor command bits [11:8] will be used; for a 136-bit search, bits [15:8] will be used and for a 272-bit search, bits [23:8] will be used. The indices for SSR, GMR, and comparand register are stored in the command word also. (For further explanation of these indices, refer to data sheets for the CYNSE70XXX NSEs.) Successive search operations are pipelined. For a 64-bit network processor interface running at 100 MHz, the NDC can sustain 33 Msps for tables configured as x68 bit in the NSEs. For x136-bit CFG, the performance will be 25 Msps, and for x272-bit CFG, the peak performance will be 16.67 Msps. For a 32-bit network processor Interface, the peak performance will drop by a factor of one half compared to the performance of the 64-bit interface. 7.3.2 Context Descriptor Data 0-Data 3
For the Search command these words contain the search key that will be presented to the NSEs. Table 7-6 shows the meaningful fields for each search size that are driven on the NSE bus DQ from the descriptors.The data driven on the DQ[3:0] for various searches is picked from the command word as follows. 68-bit search: layer attribute and valid bits for Data 0. 136-bit search: layer attribute and valid bits for Data 0 and Data 1. 272-bit search: layer attribute and valid bits for Data 0, Data 1, Data 2, and Data 3. Table 7-6. Search Data Search Size 00 01 10 11 Meaningful Data (64 bits each) Data 0 --> DQ[67:4] (Cycle A and B) Data 0 --> DQ[67:4] (Cycle A), Data 1 --> DQ[67:4] (Cycle B) Data 0 --> DQ[67:4] (Cycle A), Data 1 --> DQ[67:4] (Cycle B) Data 2 --> DQ[67:4] (Cycle C), Data 3 --> DQ[67:4] (Cycle D) Reserved
Result Registers 0 and 1 return the result of the search operation. Learn Command (03H). The Learn command's structure is le(indx). The Learn command will use two 64-bit words (command descriptor word and Data 0) in the context descriptor. The command includes an index for a Comparand register of the NSE, where the data to be Learnt was stored by a prior search instruction. Data 0 contains the data to be written in associative SRAM. Learn will result in error if the Learn is performed when the NSE SE_FULL is high. The error bit in the result register will indicate the error. The Learn error will be set in the error and status register. Move Command (04 H). The Move command's structure is mv(addr1, addr2, len). The Move command utilizes two 64-bit words in the context descriptor: command descriptor word, and Data 0 word. Bits 15-0 of the Data 0 word will contain the source address; bits 23-19 will contain the SEID; bits 39-24 will contain the destination address, bits 47-43 will contain the destination SEID; and bits 56-48 will contain the move block length (see Table 7-7). Current implementation restricts the maximum move block length to 256 words (of 68-bit each) in between/within the NSE(s). The minimum length for the Move command is four locations. Document #: 38-02043 Rev. *B Page 18 of 42
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Table 7-7. Move Command Parameters ADR 63-57 56-48 47-43 42-40 39-24 Destination Address Pointer 23-19 Source SEID 18-16 Reserved 15-0 Source Address Pointer Data 0 Reserved Move Length Destination Reserved SEID
For Move instruction, Data 0 is used to pass the source address pointer and SEID, destination address pointer and the SEID, and the number of x68 entries to be moved move/swap length. The NDC implements the Move instruction as Burst Read and then a Burst Write into the NSEs. Swap Command (05H). The Swap command's structure is sw(addr1, addr2, len). The Swap command will use two 64-bit words in the context descriptor: command word, and Data 0 word. Bits 15-0 of the Data 0 word will contain the first address; bits 23-19 will contain the first SEID; bits 39-24 will contain the second address, bits 47-43 will contain the second SEID; and bits 56-48 will contain the Swap block length (see Table 7-8). The maximum Swap block length is 128 words (of 68-bit each) in the NSE. The minimum length for Swap is four locations. Table 7-8. Swap Command Parameters ADR Data 0 63-7 Reserved 56-48 Swap Length 47-43 Second SEID 42-40 Reserved 39-24 Second Address Pointer 23-19 First SEID 18-16 Reserved 15-0 First Address Pointer
For Swap instruction, Data 0 is used to pass the first address pointer and SEID, the second address pointer and SEID, and the number of x68 entries to be swapped. The NDC implements the Swap instruction as two burst Reads and then two burst Writes into the NSEs. Note. The Move and Swap commands will not work across the NSE boundaries if several NSEs are cascaded. 7.3.3 SSRAM Read/Write
For SSRAM (connected to the NSE) Read or Write operations, Data 0 is used to pass the SSRAM address and SEID. Data 1 is used for passing the data for a Write operation. Table 7-9 shows the format for Data 0 and Data 1 for accessing the SSRAM. Table 7-9. SSRAM Data ADR Data 0 Data 1 63-24 Reserved 23-19 SEID Data[63:0] 18-16 Reserved 15-0 Address[15:0]
For NSE Read and Write operations, the Data 0 is used to pass address and SEID. Data 1 is used for passing data for Write operations. This 64-bit Data 1 field holds data[67:4] for the NSE, while data[3:0] is held in the layer attribute and valid bits field of the command descriptor word. The NSE operation can be on the array, mask array, or the command registers. Table 7-10 shows the format for Data 0 and Data 1 for accessing the NSE data, mask, and register locations. Table 7-10. NSE Data, Mask, and Register Locations ADR Data 0 Data 1 7.3.4 Result Register 0 and 1 for Read Operation 63-24 Reserved 23-19 SEID Data[67:4] 18-16 Reserved 15-0 Address[15:0]
These two registers return the result of the Read operation in two 64-bit words. Result Register 0 contains the four least significant bits of data (layer attribute/valid bits) and the status of Read operation along with the processor and context ID. This is shown in Table 7-11. Table 7-11. Read Response at Result Register 0 Bit Positions 7 63-56 55-48 47-40 39-32 31-24 Done Reserved Reserved 6 Associative Data SSRAM Connected to Coprocessor Bus 5 4 Reserved Reserved Reserved Processor ID[4:0] Context ID [4:0] 3 2 1 0
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Table 7-11. Read Response at Result Register 0 (continued) Bit Positions 23-16 15-8 7-0 Reserved Associative Data SSRAM Connected to Coprocessor Bus Reserved Reserved SE Data[3:0]
Processor ID[4:0]. The processor ID from the command descriptor is identified here. Context ID[4:0]. The context ID from the command descriptor is identified here. Done. This field indicates that the Read operation is complete. When the done bit is set, the next command can be written in the descriptor. The done bit is cleared when the Result Register 0 is Read by the network processor. SE Data[3:0]. This field contains the least four significant bits (layer attribute/valid bits) Read from the NSE 68-bit word. (This field is valid only when Reads are done from the NSE.) Result Register 1 contains the SE Data[67:4] Read from the NSE (Table 7-12) or Data[63:0] Read from the SSRAM connected to the NSE (Table 7-13). Table 7-12. Data Read from NSE ADR Result 1 Table 7-13. Data Read from SSRAM ADR Result 1 7.3.5 63-0 SSRAM Data[63:0] 63-0 SE Data[67:4]
Result Register 0 and 1 for Write/Move/Swap/Learn Operations
Only Result Register 0 carries meaningful data, as is shown in Table 7-14 below. Table 7-14. Write/Move/Swap/Learn Results Register 0 Bit Positions 7 63-56 55-48 47-40 39-32 31-24 23-16 15-8 7-0 Done Reserved Reserved Reserved Reserved Reserved Reserved 6 Associative Data SSRAM Connected to Coprocessor Bus 5 4 Reserved Reserved Reserved Reserved Reserved 3 2 1 0
Done. This field indicates that the command has been processed. When the done bit is set, the next command can be written in the descriptor. The done bit is cleared when the Result Register 0 is Read by the network processor. Result Register 1 is not used for Write/Move/Swap/Learn commands. 7.3.6 Result Register 0 and 1 for Search Operation (Case 1)
For the search operation where an SSRAM is connected to the NSE (Figure 7), the Result Register 0 carries search status, processor ID and context ID and is shown in Table 7-15. The associative data is returned in Result Register 1 if the search succeeded, as shown in Table 7-16. In addition, if the search result in data field bit in the CFG register is set, then bit[63] of Result Register 1 indicates a search success (bit[63] = 1) or search failure (bit[63] = 0). In this case bits 62-0 contain the 63-bit associative data from the SSRAM, as is shown in Table 7-17.
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Table 7-15. Result Register 0 for Search Operation Bit Positions 7 63-56 55-48 47-40 39-32 31-24 23-16 15-8 7-0 Done Reserved Hit Reserved Reserved Reserved Reserved 6 5 SE Data/Mask Array access Results 4 Reserved Reserved Reserved Processor ID [4:0] Context ID [4:0] 3 2 1 0
Processor ID[4:0]. The processor ID from the command descriptor is identified here. Context ID[4:0]. The context ID from the command descriptor is identified here. Hit. The hit flag indicates whether the search was successful. Done. This field indicates that the command has been processed. The done bit is cleared when the Result Register 0 is Read by the network processor. A new command can be initiated by the network processor through this descriptor after the done bit has cleared. Table 7-16. Result Register 1 (Search Result Bit in Data Field = 0) ADR Result 1 Table 7-17. Result Register 1 (Search Result Bit in Data Field = 1) ADR Result 1 7.3.7 Hit 63-0 Associative Data[62:0] 63-0 Associative Data[63:0]
Result Register 0 and 1 for Search Operation (Case 2)
For the search operation where the SSRAM is connected to the network processor (see Figure 13-1), the Result Register 0 carries the search response (see Table 7-18) and result register 1 is unused. Table 7-18. Search Response in Result Register 0 (type I) Bit Positions 7 63-56 55-48 47-40 39-32 31-24 23-16 15-8 7-0 Reserved Done Hit Reserved Reserved Index [23:16] Index [15:8] Index [7:0] 6 Associative Data SSRAM connected to Coprocessor Bus 5 4 Reserved Reserved Reserved Processor ID[4:0] Context ID [4:0] 3 2 1 0
Processor ID[4:0]. The processor ID set in the command descriptor is set here. Context ID[4:0]. The context ID set in the command descriptor is set here. Hit. The hit flag indicates whether the search was successful. Done. This field indicates that the command has been processed. The done bit is cleared when the Result Register 0 is Read by the network processor. A new command can be initiated by the network processor through this descriptor after the done bit has cleared.
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Index. This field contains index returned by the NSEs where a successful hit was found. This field is valid only if the hit bit in the Result Register 0 is a 1. Table 7-19 below shows the number of index bits for various NSEs. Note. CYNSE70032 and CYNSE70064 bits 23-22 of the index will always be 00. (Refer to the specifications of the CYNSE70XXX for the description of the index returned by the NSEs.) Table 7-19. Index Bits for NSEs Device CYNSE70032 CYNSE70064 CYNSE70128 SAP 21:19 21:20 23:21 SEID 18:14 19:15 20:16 Index 13:0 14:0 15:0
Note. SAP is the SSRAM Address (SADR) Prefix. These bits are passed along with the command descriptor word in the SAP field. 7.3.8 Functional Overview of Context Descriptor
The network processor(s) can Write up to 32 contexts. There can be up to 32 operations in flight through the database coprocessing subsystem. If 30 descriptor entries are in use, the NDC will issue the DESC_AFUL signal to inform that command descriptor ring is almost full. The database coprocessor continually executes the commands posted in the descriptors. The commands are executed and the results written in the Result Registers 0 and 1 of the corresponding descriptor entries. The network processor(s) will Read the results and free the descriptor entry for another command. The handshake for the command handoff from the network processor uses the start bit in the command descriptor. The network processor will load the command and the associative parameter along with the start bit in the descriptors. As the start bit in a descriptor is set, the NDC will take the command and insert it in the pipeline queue for execution. The commands in the pipeline queue are strictly handled in a first-in, first-out manner. Note. The network processor must make sure that the start bit is set in the last access to the descriptor to complete the command. The commands from the pipeline queue are continually executed by the NDC and the results are loaded back to the command initiating descriptor's Result Registers 0 and 1. The handshake for the results from the NDC back to network processor is done through any of the following mechanisms: * Done bit * CPID bus, STRB signal. In the first method, after the network processor has issued a command to the NDC, the network processor will continually poll that command descriptor entry for the done bit. Once done bit is set, it signals to the network processor that the results are Ready in Results Registers 0 and 1 for Readout. Reading of these registers by the network processor will clear the done bit. This descriptor entry is free and may now be used for another command. In the second method, the network processor uses the interrupt mechanism for Reading the command results. After the results are Ready in Result Registers 0 and 1 and the done bit is set, the NDC will assert pins CPID[7:0] (with the concatenated processor and context ID information) and activate the STRB signal for one CLK cycle. This STRB signal interrupts and the CPID identifies the context and/or processor for which the result are Ready. The context within that processor can wake up and Read the results (Result Register 0 and 1) from the appropriate descriptor. Reading of these registers by the network processor will reset the done bit. This descriptor entry is free and may now be used for another command.
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8.0 NDC Subsystem Power-up Initialization Procedure
On power-up (boot), the network processor will apply the following sequence of operations. 1. Write SRST and CFG information to 1 in the CFG register. 2. Wait at least 32 cycles, then poll on SRST. 3. Write the CFG registers to each of the NSEs, starting with the one residing at the least significant address. 4. Write the CFG registers of the last NSE in the depth-cascaded system, setting the LDEV and LRAM bits to a 1. 5. The descriptor block is now Ready for use by the network processor(s) for building, managing, and/or searching the database. Hardware Interface Timing Protocols--NDC Interface. The network processor interface of the NDC supports a variety of SSRAM interfaces. It supports both SyncBurst as well as ZBT SSRAMs. IFC_CFG[2:0] pins select the interface type for the device as follows. (Refer to SSRAM specifications and application notes from such vendors as IDT and Micron.) 000: ZBT pipelined mode 001: ZBT flowthrough mode 010: SyncBurst pipelined mode (early Write) 011: SyncBurst pipelined mode (late Write) 100-111: Reserved.
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9.0 ZBT Pipelined SSRAM Interface Mode
The ADR and control signals (R/W_L, BW_L[7:0], CE_L, CE2, CE2_L) are sampled on a CLK edge. For Write cycles, the data is sampled two cycles later; for Read cycles, the data is available to the processor two cycles later. Both Write- and Read-cycle latency is two cycles and there is no gap required between Read and Write operations. Every cycle is available for the network processor(s) for full utilization of the bus bandwidth. See Figure 9-1. Note. BWE_L is not used in this mode and should be tied inactive.
1 CLK ADR[9:0] BW_L[7:0] A1
2
3
4
5
6
7
A2
A3
A4
A5
A6
DATA[63:0] CE_L
D1
Q2
D3
D4
Q5
CE_2 R/W_L
STRB CPID[7:0] CPID Write Read Write Write Read Read
Figure 9-1. ZBT Pipelined SRAM Interface (Mode 000)
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10.0 ZBT Flowthrough SSRAM Interface Mode
The ADR and control signals (R/W_L, BW_L[7:0], CE_L, CE2, CE2_L) are sampled on a CLK edge. For Write cycles, the data is sampled one cycle later; for Read cycles, the data is available to the processor one cycle later. Both Write- and Read-cycle latency is one cycle, and there is no gap required between Read and Write operation. Every cycle is available for the network processor(s) for full utilization of the bus bandwidth. See Figure 10-1. Note. BWE_L is not used in this mode and should be tied inactive. 1 CLK ADR[9:0] BW_L[7:0] A1 A2 A3 A4 A5 2 3 4 5 6 7
DATA[63:0] CE_L
D1
Q2
D3
Q4
Q5
CE_2 CE2_L
R/W_L
STRB CPID[7:0] CPID Write Read Write Write Read
Figure 10-1. ZBT Flowthrough SSRAM Interface (Mode 001)
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11.0 SyncBurst Pipelined SSRAM Interface (Early Write)
The ADR and control signals (R/W_L, BW_L[7:0], CE_L, CE2, CE2_L) are sampled on a CLK edge. For Write cycles, the data is sampled one cycle later; for Read cycles, the data is available to the processor one cycle later. Both Write- and Read-cycle latency is one cycle, and there is no gap required between Read and Write operation. Every cycle is available for the network processor(s) for full utilization of the bus bandwidth. See Figure 11-1. Note. BWE_L is not used in this mode and should be tied inactive.
1 CLK ADR[9:0] BW_L[7:0] A1
2
3
4
5
6
7
8
A2
A3
A4
A5
DATA[63:0] CE_L
D1
Q2
D3
Q4
CE_2 R/W_L STRB CPID[7:0] CPID Write Read NOP Write Read
Figure 11-1. SyncBurst Pipelined SSRAM Interface (Early Write)
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12.0 SyncBurst Pipelined SSRAM Interface Mode (Late Write)
The ADR and control signals (R/W_L, BW_L[7:0], CE_L, CE2, CE2_L) are sampled on a CLK edge. For Write cycles, the data is sampled one cycle later; for Read cycles, the data is available to the processor one cycle later. Both Write- and Read-cycle latency is one cycle, and there is no gap required between Read and Write operation. Every cycle is available for the network processor(s) for full utilization of the bus bandwidth. See Figure 12-1. Note. BWE_L is not used in this mode and should be tied inactive. 1 CLK ADR[9:0] BW_L[7:0] A1 A2 A3 A4 A5 2 3 4 5 6 7 8
DATA[63:0] CE_L
D1
Q2
D3
Q4
Q5
CE_2 R/W_L STRB CPID[7:0] CPID Write Read NOP Write Read
Figure 12-1. SyncBurst Pipelined SSRAM Interface (Late Write)
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13.0 Application Information
There are two ways to build a database coprocessing subsystem using CYNPC80192, CYNSE70XXX, and SSRAMs. In the first system the associative data SSRAMs are connected to the coprocessor and the NSE (Figure 13-1) and the coprocessor returns the associated data in response to a search operation. This type of implementation is suited to applications where the associative data size is up to eight bytes. Coprocessor NSE Bank SSRAM Bank
Figure 13-1. Configuration 1--Associative SSRAM Mode In the second system, the coprocessor returns the index of the successful search entry. The network processor uses the index as the page offset to access the associative data from SSRAM directly (see Figure 13-2). This implementation is suited to applications where the associative data size is longer than eight bytes.
Coprocessor
NSE Bank
SSRAM Bank Figure 13-2. Configuration 2--Index Mode Single or multiple network processors with the arbitration to the SRAM interface can access the database coprocessing subsystem to implement a parallel packet processing system, as shown in Figure 13-3.
Network Processors
Coprocessors
Network Processors
SSRAMs
Figure 13-3. Switching Systems Block Diagram
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14.0 Information on External Transceivers
As more NSEs are added to the DQ bus, the capacitive load on the bus increases, reducing the bus speed. CYNSE80192 gets around this by using external transceivers, and provides a glueless support to add the transceivers (Phillips 74ALVT16652) between a bank of NSEs and the CYNPC80192 (see Figure 14-1). Transceivers CLK (System Clock)
XVER_0 XVER_0_L CYNPC80192 Transceivers XVER_1 XVER_1_L
XVER_2 Transceivers
XVER_2_L Figure 14-1. Use of Transceiver Enables The XVER_0, XVER_1, and XVER_2 are electrically buffered versions of the same logical signal in the CYNPC80192 device. The XVER_0_L, XVER_1_L, and XVER_2_L are also electrically buffered versions of the same logical signal in the CYNPC80192 device. Multiple copies of these signals are provided in order to increase the ability of the signal to drive many transceiver devices of eight-bit width. Figure 14-2 shows one example of the distribution of signals driving the transceivers. Transceivers CYNCP80192 NSEs
SSRAM Figure 14-2. Transceiver Connected Between CYNPC80192 and CYNSE70XXX Devic-
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15.0 JTAG (1149.1) Testing
The CYNPC80192 supports the Test Access Port and Boundary Scan Architecture as specified in the IEEE JTAG Standard 1149.1. The pin interface to the chip consists of five signals with the standard definitions: TCK, TMS, TDI, TDO, and TRST_L. Table 15-1 and Table 15-2 describe the operations that the test access port controller supports and the test access port device ID register. Table 15-1. Test Access Port Controller Instructions Instruction Type Description SAMPLE/PRELOAD Mandatory Sample/Preload. Loads the values of signals going to and from I/O pins into the boundary scan shift register to provide a snapshot of the normal functional operation. EXTEST INTEST Mandatory External Test. Uses boundary scan values shifted in from TAP to test connectivity external to the device. Optional Internal Test. Allows slow-speed functional testing of the device using the boundary scan register to provide the I/O values.
Table 15-2. Test Access Port Device ID Register Field Revision Range [31:28] Initial Value 0001 Description Revision Number. This is the current device revision number. Numbers start from one and increment by one for each revision of the device. Manufacturer ID. This field is the same as the manufacturer ID used in the TAP controller. Least Significant Bit.
Part Number [27:12] 0000 0000 0000 0011 This is the part number for this device. MFID LSB [11:1] 0 000_1101_1100 1
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CYNCP80192
16.0 Electrical Characteristics
This section describes the electrical specifications, capacitance, operating conditions, DC characteristics, and AC timing parameters for the NDC (see Table 16-1, Table 16-2, Table 16-3, Table 16-4, and Table 16-5). Table 16-1. Electrical Characteristics Parameter ILI ILO VOL VOH ICC_core Description Input Leakage Current Output Leakage Current[9] Output Low Voltage Output High Voltage 2.5 V Supply Current[10] Test Conditions 0 < VIN < VDDQ 0 < VOUT < VDDQ 8 mA, VDDQ = 3.3V 4 mA, VDDQ = 3.3V 2.4 TBD TBD Description Input Capacitance Max. TBD TBD Min. 3.14 2.37 2.0 -0.3 0 -5% Max. 3.45 2.63 VDD+0.3 0.8 70 +5% Min. -10 -10 Max. 10 10 0.4 Unit uA uA V V mA mA Unit pF[11] pF[12] Unit V V V V C
3.3 V Supply Current ICC_IO Table 16-2. Capacitance Parameter CIN COUT Output Capacitance Table 16-3. Operating Conditions Parameter VDDQ VDD VIH VIL TA Description Operating Voltage for IO Operating Supply Voltage Input High Voltage[13] Input Low Voltage[14] Ambient Operating Temperature Supply Voltage Tolerance
Table 16-4. AC Timing Parameters for Pipelined ZBT SSRAM and SyncBurst SSRAM Parameter TCLK TCKHI TCKLO TSA THA TCKOV TCK2X TCLKPHSL TCKSE TSCK TCKSD TCKOLZ TCKOHZ Description CLK period: max frequency CLK high pulse; worst-case 40%-60% duty cycle[15] CLK low pulse; worst-case 40%-60% duty cycle[15] Set-up Time to CLK rising edge[16] 30 Hold Time to CLK rising edge[17] Clock to output valid (Network Processor Interface) Clock to CLK2X delay Clock to PHS_L delay Clock to output valid (NSE Interface) Clock to SCLK delay Clock to output valid (SDATA) Clock to output in Low-Z Clock to output in High-Z 20 3 6 40 4.0 4.0 2.5 1.5 8.0 3.5 6 9 5 10 3 7 Test Conditions Load (pF) CYNPC80192-100 CYNPC80192-83 Min. Max. 100 4.8 4.8 3.0 1.5 9.0 4.0 7 11 6 12 Min. Max. 83 Unit MHz ns ns ns ns ns ns Ns ns ns ns ns ns
Notes: 9. Applies only for outputs in three-state. 10. Average operating current at maximum frequency. Transient peak currents may exceed these values. 11. f = 1 MHz, VIN = 0V. 12. f = 1 MHz, VOUT - 0V. 13. Maximum allowable applies to overshoot only (VDDQ is 3.3V supply). 14. Minimum allowable applies to undershoot only. 15. 1. TCLKHI and TCLKO duty-cycle values are based on 20-80% signal levels. 16. 2. Set-up time for ADR, CLK enable, data, Read/Write, CE, and byte Write enable. 17. 3. Hold time for ADR, CLK enable, data, Read/Write, CE, and byte Write enable.
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CYNCP80192
Table 16-5. AC Timing Parameters for ZBT and Flow-Through SSRAM Parameter TCLK TCKHI TCKLO TSA THA TCKOV TCLK2 TCLKPHSL TCKSE TSCK TCKSD TCKOLZ TCKOHZ Description CLK period: max frequency CLK high pulse; worst-case 40%-60% duty cycle CLK low pulse; worst-case 40%-60% duty cycle Address setup time to CLK rising edge Address hold time to CLK rising edge Clock to output valid (network processor interface) Clock to CLK2X delay Clock to PHS_L delay Clock to output valid (NSE Interface) Clock to SCLK delay Clock to output valid (SDATA) Clock to output in low-Z Clock to output in high-Z 20 3 7 40 30 8 8 6 2 18 4 7 12 6 13 Test Conditions Load (pF) CYNPC80192-83 Min Max 50 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns
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CYNCP80192
AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Data 2 STRB CBID1 BIG_LT L_L CPID4 IFC_CF G2 TCK CPID7 DESC_ AFULL TDO CMD1 CMD4 CMD7 CMD8 DQ1 DQ4 DQ7 DQ10 DQ13 DQ15 DQ18 DQ21 DQ24 XVER_0 _L DQ28 DQ31
AE
DATA5 Data 1 CPID0 CPID2 IFC_CF G0 CPID5 TDI CPID6 CAM_F ULL CLK2X CMD0 CMD3 CMD6 CMDV DQ2 DQ5 DQ8 DQ11 DQ14 DQ17 DQ20 DQ23 XVER_0 DQ27 DQ30 DQ34
AD
DATA6 Data 3 Data 0 IRST_L IWIDTH CPID3 IFC_CF G1 TMS TRST_L PHS_L ORST_ L CMD2 CMD5 DQ0 DQ3 DQ6 DQ9 DQ12 DQ16 DQ19 DQ22 DQ25 DQ26 DQ29 DQ33 DQ35
AC
DATA9 DATA7 DATA4 GND VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ GND GND VDDQ VDDQ VDDQ VDDQ VDDQ VDD VDD VDD GND DQ32 DQ36 DQ38
AB
Data 12 Data 10 DATA8 VDD
AA
Data 15 Data 13 Data 11 VDD
Y
Data 18 Data 16 Data 14 VDD
W
Data 21 Data 19 Data 17 VDDQ
V
Data 23 Data 22 Data 20 VDDQ
U
Data 26 Data 25 Data 24 VDDQ
T
BW_L6 BW_L7 Data 27 VDDQ
R
BW_L3 BW_L4 BW_L5 VDDQ
P
BW_L2 CLK XVER_2 _L GND
N
BW_L1 BW_L0 ADR0 GND
M
ADR1 ADR2 ADR3 VDDQ
L
ADR4 ADR5 ADR6 VDDQ
K
ADR7 ADR8 ADR9 VDDQ
J
CE2 CE_L CE2_L VDDQ
H
RW_L OE_L Data 28 VDD
G
BWE_L Data 29 Data 31 VDD
F
Data 30 Data 32 Data 34 VDD
E
Data 33 Data 35 Data 37 VDD
D
Data 38 DATA4 0 GND VDD VDD VDD VDDQ VDDQ VDDQ
C
DATA4 1 GND DATA4 6 DATA4 9 DATA5 2 DATA5 5 DATA5 8 DATA6 2 SCANE XVER_ 2 DQ_72 SDATA 63 SDATA 58 SDATA 55 SDATA 52 SDATA 49 SDATA 45 SDATA 42 SData 39 SData 36 SData 33 SData 28 SData 25 SData 23 SData 21
B
DATA4 2 GND DATA4 5 DATA4 8 DATA5 1 DATA5 4 DATA5 7 DATA6 0 DATA6 3 SCAN M XVER_ 1_L SCLK SDATA 62 SDATA 59 SDATA 56 SDATA 53 SDATA 50 SDATA 47 SDATA 44 SDATA 41 SData 38 SData 35 SData 32 SData 29 SData 26 SData 24
A
DATA4 3 DATA4 4 DATA4 7 DATA5 0] DATA5 8 DATA5 6 DATA5 9 DATA6 1 INTR TESTM XVER_ 1 SOE_L SDATA 61 SDATA 60 SDATA 57 SDATA 54 SDATA 51 SDATA 48 SDATA 46 SDATA 43 SDATA 40 SData 37 SData 34 SData 31 SData 30 SData 27
Data 36 Data 39
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21
VDD VDD GND GND VDD VDD
VDD GND GND GND GND VDD
GND GND GND GND GND GND
GND GND GND GND GND GND
VDD GND GND GND GND VDD
VDD VDD GND GND VDD VDD
VDDQ VDDQ GND GND VDDQ VDDQ VDDQ VDDQ VDDQ VDD VDD VDD
22 23 24 25 26
VDD DQ37 DQ39 DQ40
VDD FULL DQ41 DQ43
VDD DQ42 DQ44 DQ45
VDDQ SSV DQ46 DQ48
VDDQ DQ47 DQ49 SSF
VDDQ DQ50 DQ51 DQ52
VDDQ DQ53 DQ54 EOT
VDDQ DQ55 DQ56 DQ57
GND DQ58 DQ59 ACK
GND DQ61 DQ62 DQ60
VDDQ DQ65 DQ64 DQ63
VDDQ SData 0 DQ67 DQ66
VDDQ SData 3 SData 2 SData 1
VDDQ SDATA6
VDD SData 10
VDD SData 13 SData 11
VDD SData 16 SData 14 SData 12
VDD SData 19 SData 17 SData 15
GND SData 22 SData 20 SData 18
SDATA5 SDATA8
SDATA4 SDATA7 SDATA9
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Figure 16-1. Pinout Diagram
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CYNCP80192
Table 16-6 contains an alphabetical listing of the pins marked out in Figure 16-1, above. Table 16-6. CYNPC80192 Pinout Description Package Ball Number A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 A24 A25 A26 A3 A4 A5 A6 A7 A8 A9 AA1 AA2 AA23 AA24 AA25 AA26 AA3 AA4 AD1 AD10 AD11 AD12 AD13 AD14 AD15 AD16 Signal Name DATA[43] TESTM XVER_1 SOE_L SDATA[61] SDATA[60] SDATA[57] SDATA[54] SDATA[51] SDATA[48] SDATA[46] DATA[44] SDATA[43] SDATA[40] SDATA[37] SDATA[34] SDATA[31] SDATA[30] SDATA[27] DATA[47] DATA[50] DATA[53] DATA[56] DATA[59] DATA[61] INTR DATA[15] DATA[13] VDD FULL DQ[41] DQ[43] DATA[11] VDD DATA[06] PHS_L ORST_L CMD[2] CMD[5] DQ[00] DQ[03] DQ[06] Signal Type I/O Input Output Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output I/O I/O 2.5 Volts Input I/O I/O I/O 2.5 Volts I/O Output Output Output Output I/O I/O I/O Package Ball Number AB1 AB2 AB23 AB24 AB25 AB26 AB3 AB4 AC1 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC2 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AE19 AE2 AE20 AE21 AE22 AE23 AE24 AE25 Signal Name DATA[12] DATA[10] VDD DQ[37] DQ[39] DQ[40] DATA[08] VDD DATA[09] VDDQ VDDQ VDDQ VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ DATA[07] VDD VDD VDD VSS DQ[32] DQ[36] DQ[38] DATA[04] VSS VDD VDD VDD VDDQ VDDQ DQ[14] DATA[01] DQ[17] DQ[20] DQ[23] XVER_0 DQ[27] DQ[30] Signal Type I/O I/O 2.5 Volts I/O I/O I/O I/O 2.5 Volts I/O 3.3 Volts 3.3 Volts 3.3 Volts Ground Ground 3.3 Volts 3.3 Volts 3.3 Volts 3.3 Volts 3.3 Volts I/O 2.5 Volts 2.5 Volts 2.5 Volts Ground I/O I/O I/O I/O Ground 2.5 Volts 2.5 Volts 2.5 Volts 3.3 Volts 3.3 Volts I/O I/O I/O I/O I/O Output I/O I/O Page 34 of 42
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CYNCP80192
Table 16-6. CYNPC80192 Pinout Description (continued) Package Ball Number AD17 AD18 AD19 AD2 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AE1 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AF4 AF5 AF6 AF7 AF8 AF9 B1 B10 B11 B12 B13 B14 B15 B16 B17 Signal Name DQ[09] DQ[12] DQ[16] DATA[03] DQ[19] DQ[22] DQ[25] DQ[26] DQ[29] DQ[33] DQ[35] DATA[00] IRST_L IWIDTH CPID[3] IFC_CFG[1] TMS TRST_L DATA[05] CLK2X CMD[0] CMD[3] CMD[6] CMDV DQ[02] DQ[05] DQ[08] DQ[11] BIG_LTL_L CPID[4] IFC_CFG[2] TCK CPID[7] DESC_AFULL DATA[42] SCANM XVER_1_L SCLK SDATA[62] SDATA[59] SDATA[56] SDATA[53] SDATA[50] Signal Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input Output Input Input Input I/O Output Output Output Output Output I/O I/O I/O I/O Input Output Input Input Output Output I/O Input Output Output I/O I/O I/O I/O I/O Package Ball Number AE26 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF3 C13 C14 C15 C16 C17 C18 C19 C2 C20 C21 C22 C23 C24 C25 C26 Signal Name DQ[34] CPID[0] CPID[2] IFC_CFG[0] CPID[5] TDI CPID[6] CAM_FULL DATA[02] TDO CMD[1] CMD[4] CMD[7] CMD[8] DQ[01] DQ[4] DQ[07] DQ[10] DQ[13] STRB DQ[15] DQ[18] DQ[21] DQ[24] XVER_0_L DQ[28] DQ[31] CPID[1] SDATA[63] SDATA[58] SDATA[55] SDATA[52] SDATA[49] SDATA[45] SDATA[42] DATA[41] SDATA[39] SDATA[36] SDATA[33] SDATA[28] SDATA[25] SDATA[23] SDATA[21] Signal Type I/O Output Output Input Output Input Output Output I/O Output Output Output Output Output I/O I/O I/O I/O I/O Output I/O I/O I/O I/O Output I/O I/O Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
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CYNCP80192
Table 16-6. CYNPC80192 Pinout Description (continued) Package Ball Number B18 B19 B2 B20 B21 B22 B23 B24 B25 B26 B3 B4 B5 B6 B7 B8 B9 C1 C10 C11 C12 D22 D23 D24 D25 D26 D3 D4 D5 D6 D7 D8 D9 E1 E2 E23 E24 E25 E26 E3 E4 F1 F2 Signal Name SDATA[47] SDATA[44] VSS SDATA[41] SDATA[38] SDATA[35] SDATA[32] SDATA[29] SDATA[26] SDATA[24] DATA[45] DATA[48] DATA[51] DATA[54] DATA[57] DATA[60] DATA[63] DATA[39] SCANE XVER_2 DQ_72 VDD VSS SDATA[22] SDATA[20] SDATA[18] DATA[40] VSS VDD VDD VDD VDDQ VDDQ DATA[33] DATA[35] VDD SDATA[19] SDATA[17] SDATA[15] DATA[37] VDD DATA[30] DATA[32] Signal Type I/O I/O Ground I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Output I/O 2.5 Volts Ground I/O I/O I/O I/O Ground 2.5 Volts 2.5 Volts 2.5 Volts 3.3 Volts 3.3 Volts I/O I/O 2.5 Volts I/O I/O I/O I/O 2.5 Volts I/O I/O Package Ball Number C3 C4 C5 C6 C7 C8 C9 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 H1 H2 H23 H24 H25 H26 H3 H4 J1 J2 J23 J24 J25 J26 J3 J4 K1 K2 K23 K24 K25 K26 Signal Name VSS DATA[46] DATA[49] DATA[52] DATA[55] DATA[58] DATA[62] DATA[36] VDDQ VDDQ VDDQ VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ DATA[38] VDD VDD RW_L OE_L VDD SDATA[10] SDATA[08] SDATA[07] DATA[28] VDD CE2 CE_L VDDQ SDATA[06] SDATA[05] SDATA[04] CE2_L VDDQ ADR[7] ADR[8] VDDQ SDATA[03] SDATA[02] SDATA[01] Signal Type Ground I/O I/O I/O I/O I/O I/O I/O 3.3 Volts 3.3 Volts 3.3 Volts Ground Ground 3.3 Volts 3.3 Volts 3.3 Volts 3.3 Volts 3.3 Volts I/O 2.5 Volts 2.5 Volts Input Input 2.5 Volts I/O I/O I/O I/O 2.5 Volts Input Input 3.3 Volts I/O I/O I/O Input 3.3 Volts Input Input 3.3 Volts I/O I/O I/O
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CYNCP80192
Table 16-6. CYNPC80192 Pinout Description (continued) Package Ball Number F23 F24 F25 F26 F3 F4 G1 G2 G23 G24 G25 G26 G3 G4 L3 L4 M1 M11 M12 M13 M14 M15 M16 M2 M23 M24 M25 M26 M3 M4 N1 N11 N12 N13 N14 N15 N16 N2 N23 N24 N25 N26 N3 Signal Name VDD SDATA[16] SDATA[14] SDATA[12] DATA[34] VDD BWE_L DATA[29] VDD SDATA[13] SDATA[11] SDATA[09] DATA[31] VDD ADR[6] VDDQ ADR[1] VDD VSS VSS VSS VSS VDD ADR[2] VDDQ DQ[65] DQ[64] DQ[63] ADR[3] VDDQ BW_L[1] VSS VSS VSS VSS VSS VSS BW_L[0] VSS DQ[61] DQ[62] DQ[60] ADR[0] Signal Type 2.5 Volts I/O I/O I/O I/O 2.5 Volts Input I/O 2.5 Volts I/O I/O I/O I/O 2.5 Volts Input 3.3 Volts Input 2.5 Volts Ground Ground Ground Ground 2.5 Volts Input 3.3 Volts I/O I/O I/O Input 3.3 Volts Input Ground Ground Ground Ground Ground Ground Input Ground I/O I/O I/O Input Package Ball Number K3 K4 L1 L11 L12 L13 L14 L15 L16 L2 L23 L24 L25 L26 P16 P2 P23 P24 P25 P26 P3 P4 R1 R11 R12 R13 R14 R15 R16 R2 R23 R24 R25 R26 R3 R4 T1 T11 T12 T13 T14 T15 T16 Signal Name ADR[9] VDDQ ADR[4] VDD VDD VSS VSS VDD VDD ADR[5] VDDQ SDATA[00] DQ[67] DQ[66] VSS CLK VSS DQ[58] DQ[59] ACK XVER_2_L VSS BW_L[3] VDD VSS VSS VSS VSS VDD BW_L[4] VDDQ DQ[55] DQ[56] DQ[57] BW_L[5] VDDQ BW_L[6] VDD VDD VSS VSS VDD VDD Signal Type Input 3.3 Volts Input 2.5 Volts 2.5 Volts Ground Ground 2.5 Volts 2.5 Volts Input 3.3 Volts I/O I/O I/O Ground Input Ground I/O I/O Input Output Ground Input 2.5 Volts Ground Ground Ground Ground 2.5 Volts Input 3.3 Volts I/O I/O I/O Input 3.3 Volts Input 2.5 Volts 2.5 Volts Ground Ground 2.5 Volts 2.5 Volts
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CYNCP80192
Table 16-6. CYNPC80192 Pinout Description (continued) Package Ball Number N4 P1 P11 P12 P13 P14 P15 U1 U2 U23 U24 U25 U26 U3 U4 V1 V2 V23 V24 V25 V26 V3 V4 Signal Name VSS BW_L[2] VSS VSS VSS VSS VSS DATA[26] DATA[25] VDDQ DQ[50] DQ[51] DQ[52] DATA[24] VDDQ DATA[23] DATA[22] VDDQ DQ[47] DQ[49] SSF DATA[20] VDDQ Signal Type Ground Input Ground Ground Ground Ground Ground I/O I/O 3.3 Volts I/O I/O I/O I/O 3.3 Volts I/O I/O 3.3 Volts I/O I/O Input I/O 3.3 Volts Package Ball Number T2 T23 T24 T25 T26 T3 T4 W1 W2 W23 W24 W25 W26 W3 W4 Y1 Y2 Y23 Y24 Y25 Y26 Y3 Y4 Signal Name BW_L[7] VDDQ DQ[53] DQ[54] EOT DATA[27] VDDQ DATA[21] DATA[19] VDDQ SSV DQ[46] DQ[48] DATA[17] VDDQ DATA[18] DATA[16] VDD DQ[42] DQ[44] DQ[45] DATA[14] VDD Signal Type Input 3.3 Volts I/O I/O Input I/O 3.3 Volts I/O I/O 3.3 Volts Input I/O I/O I/O 3.3 Volts I/O I/O 2.5 Volts I/O I/O I/O I/O 2.5 Volts
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CYNCP80192
17.0 Ordering Information
Table 17-1 provides ordering information for the CYNCP80192 device. Table 17-1. Ordering Information Part Number CYNPC80192-BGC Description Network Database Coprocessor Frequency 100 MHz Temperature Range Commercial
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CYNCP80192
18.0 Package Drawings
In the following figures the NDC package diagrams are shown from various views. Figure 18-1 shows the package from a bottom view, Figure 18-2 from a side view, and Figure 18-3 from a top view.
Figure 18-1. Package Bottom View
Figure 18-2. Package Side View
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CYNCP80192
Figure 18-3. Package Top View ZBT is a trademark of Integrated Device Technology. SyncBurst is a trademark of Micron Technology. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CYNCP80192
Document History Page
Document Title: CYNCP80192 Network Database Coprocessor Document Number: 38-02043 REV. ** *A *B ECN NO. 111444 115873 127446 Issue Date 01/29/02 05/17/02 08/29/03 Orig. of Change AFX FSG DCU New Data Sheet Typo in ordering information table (changed from CYNCP80192-100 to CYNCP80192-BGC) Clarified scope and description of BIG/LTL_L signal Clarified SSRAM feature support Corrected timing diagram for SyncBurst SSRAM interface (early write) Description of Change
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